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fn7560 rev 6.00 page 1 of 18 july 11, 2014 fn7560 rev 6.00 july 11, 2014 isl33001, isl33 002, isl33003 i2c bus buffer with rise time accelerators and hot swap capabili ty datasheet the isl33001, isl33002, isl33003 are 2-channel bus buffers that provide the buffering necessary to extend the bus capacitance beyond the 400pf maximum specified by the i 2 c specification. in addition, th e isl33001, isl33002, isl33003 feature rise time accelerator circuitry to reduce power consumption from passive bus pull-up resistors and improve data-rate performance. all devices also include hot swap circuitry to prevent corruption of the data and clock lines when i 2 c devices are plugged into a live backplane, and the isl33002 and isl33003 add level translation for mixed supply voltage applications. the isl33001, isl33002, isl33003 operate at supply voltages from +2.3v to +5.5v at a temperature range of -40c to +85c. related literature ? an1543 , ?isl33001msopeval1z, isl33002msopeval1z, isl33003msopeval1z evaluation board user?s manual? ? an1637 , ?level shifting between 1.8v and 3.3v using i 2 c buffers? features ?2 channel i 2 c compatible bi-directional buffer ? +2.3vdc to +5.5vdc supply range ? >400khz operation ? bus capacitance buffering ? rise time accelerators ? hot swapping capability ? 6kv class 3 hbm esd protection on all pins ? 12kv hbm esd protection on sda/scl pins ? enable pin (isl33001 and isl33003) ? logic level translation (isl33002 and isl33003) ? ready logic pin (isl33001) ? accelerator disable pin (isl33002) ? pb-free (rohs compliant) 8 ld soic (isl33001 only), 8 ld tdfn (3mmx3mm) and 8 ld msop packages ? low quiescent current . . . . . . . . . . . . . . . . . . . . . . . 2.1ma typ ? low shutdown current . . . . . . . . . . . . . . . . . . . . . . . . 0.5a typ applications ?i 2 c bus extender and capacitance buffering ? server racks for telecom, datacom, and computer servers ? desktop computers ? hot-swap board insertion and bus isolation summary of features part number level translation enable pin ready pin accelerator disable isl33001 no yes yes no isl33002 yes no no yes isl33003 yes yes no no figure 1. typical operating circuit figure 2. bus accelerator performance gnd sda scl +3.3v v cc2 c back plane isl33003 en v cc1 +5.0v device sda scl i 2 c device a b i 2 c time (2s/div) voltage (1v/div) 100khz i 2 c bus with 2.7k pull-up resistor and 400pf bus capacitance without buffer with buffer
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 2 of 18 july 11, 2014 ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (pb-free) pkg. dwg. # isl33001irtz 3001 -40 to +85 8 ld tdfn (0.65mm pitch) l8.3x3a isl33001irt2z 01r2 -40 to +85 8 ld tdfn (0.5mm pitch) l8.3x3h isl33001ibz 33001 ibz -40 to +85 8 ld soic m8.15 isl33001iuz 33001 -40 to +85 8 ld msop m8.118 isl33002irtz 3002 -40 to +85 8 ld tdfn (0.65mm pitch) l8.3x3a ISL33002IRT2Z 02r2 -40 to +85 8 ld tdfn (0.5mm pitch) l8.3x3h isl33002iuz 33002 -40 to +85 8 ld msop m8.118 isl33003irtz 3003 -40 to +85 8 ld tdfn (0.65mm pitch) l8.3x3a isl33003irt2z 03r2 -40 to +85 8 ld tdfn (0.5mm pitch) l8.3x3h isl33003iuz 33003 -40 to +85 8 ld msop m8.118 isl33001msopeval1z isl33001 evaluation board isl33002msopeval1z isl33002 evaluation board isl33003msopeval1z isl33003 evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl33001 , isl33002 , isl33003 . for more information on msl please see techbrief tb363 . pin configurations isl33001 (8 ld tdfn) top view isl33001 (8 ld soic, msop) top view isl33002 (8 ld tdfn) top view isl33002 (8 ld msop) top view 3 2 1 scl_in gnd 4 6 7 8 5 en v cc1 ready scl_out sda_in sda_out pad 6 7 8 5 3 2 1 4 gnd v cc1 en ready sda_in sda_out scl_in scl_out 3 2 1 gnd 4 6 7 8 5 v cc1 acc pad v cc2 scl_in scl_out sda_in sda_out 6 7 8 5 3 2 1 4 v cc2 gnd v cc1 acc sda_in sda_out scl_in scl_out
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 3 of 18 july 11, 2014 isl33003 (8 ld tdfn) top view isl33003 (8 ld msop) top view pin descriptions pin name pin number function notes v cc1 8v cc1 power supply, +2.3v to +5.5v. decouple v cc1 to ground with a high frequency 0.01f to 0.1f capacitor. v cc2 1v cc2 power supply, +2.3v to +5.5v. decouple v cc2 to ground with a high frequency 0.01f to 0.1f capacitor. in level shifti ng applications, sda_out and scl_out logic thresholds are referenced to v cc2 supply levels. connect pull-up resistors on these pins to v cc2 . isl33002 (8 ld tdfn, 8 ld msop) isl33003 (8 ld tdfn, 8 ld msop) gnd 4 device ground pin en 1 buffer enable pin. logic ?0? disables th e device. logic ?1? enables the device. logic threshold referenced to v cc1 . isl33001 (8 ld tdfn, 8 ld soic, msop) 5 isl33003 (8 ld tdfn, 8 ld msop) ready 5 buffer active ?ready? open drain logic ou tput. when buffer is active, ready is high impedance. when buffer is inactive, ready is low impedance to ground. connect to 10k pull-up resistor to v cc1 . isl33001 only acc 5 rise time accelerator enable pin. logi c ?0? disables the accelerator. logic ?1? enables the accelerator. logi c threshold referenced to v cc1 . isl33002 only sda_in 6 data i/o pins sda_out 7 scl_in 3 clock i/o pins scl_out 2 pad thermal pad should be connected to ground or floated. thermal pad; tdfn only pin configurations (continued) 3 2 1 gnd 4 6 7 8 5 v cc1 en pad v cc2 scl_in scl_out sda_in sda_out 6 7 8 5 3 2 1 4 v cc2 gnd v cc1 en scl_in scl_out sda_in sda_out
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 4 of 18 july 11, 2014 absolute maximum ratings (all voltages referenced to gnd) thermal information v cc1 , v cc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v sda_in, scl_in, sda_out, scl_out, ready. . . . . . . . . . . . . -0.3v to +7v en, acc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +(v cc1 + 0.3)v maximum sink current (sda and scl pins) . . . . . . . . . . . . . . . . . . . . 20ma maximum sink current (ready pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7ma latch-up tested per jesd78, level 2, class a . . . . . . . . . . . . . . . . . . 85c esd ratings. . . . . . . . . . . . . . . . . . . . . . see ? esd protection ? on page 5 operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c v cc1 and v cc2 supply voltage range . . . . . . . . . . . . . . . . . +2.3v to +5.5v thermal resistance ? ja (c/w) ? jc (c/w) 8 ld tdfn package ( notes 5 , 6 ) . . . . . . . . . . 47 4 (0.50mm pitch) 8 ld tdfn package ( notes 5 , 6 ) . . . . . . . . . . 48 6 (0.65mm pitch) 8 ld msop package ( notes 4 , 7 ) . . . . . . . . . 151 50 8 ld soic package ( notes 4 , 7 ) . . . . . . . . . . 120 56 maximum storage temperature range . . . . . . . . . . . . . -65c to +150c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications v en = v cc1 , v cc1 = +2.3v to +5.5v, v cc2 = +2.3v to +5.5v, unless otherwise noted ( note 8 ). boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol conditions temp (c) min ( note 9 )typ max ( note 9 )units power supplies v cc1 supply range v cc1 full 2.3 - 5.5 v v cc2 supply range v cc2 isl33002 and isl33003 full 2.3 - 5.5 v supply current from v cc1 i cc1 v cc1 = 5.5v; isl33001 only ( note 11 ) full - 2.1 4.0 ma v cc1 = v cc2 = 5.5v; isl33002 and isl33003 ( note 11 ) full - 2.0 3.0 ma supply current from v cc2 i cc2 v cc2 = v cc1 = 5.5v; isl33002 and isl33003 ( note 11 ) full - 0.22 0.6 ma v cc1 shut-down supply current i shdn1 v cc1 = 5.5v, v en = gnd; isl33001 only full - 0.5 - a v cc1 = v cc2 = 5.5v, v en = gnd; isl33003 only ( note 13 ) full - 0.05 - a v cc2 shut-down supply current i shdn2 v cc1 = v cc2 = 5.5v, v en = gnd, isl33003 only ( note 13 ) full - 0.06 - a start-up circuitry precharge circuitry voltage v pre sda and scl pins floating full 0.8 1 1.2 v enable high threshold voltage v en_h +25 - 0.5*v cc 0.7*v cc v enable low threshold voltage v en_l +25 0.3*v cc 0.5*v cc -v enable pin input current i en enable from 0v to v cc1; isl33001 and isl33003 full -1 0.1 1 a enable delay, on-off t en-hl isl33001 and isl33003 ( note 10 ) +25 - 10 - ns enable delay, off-on t en-lh isl33001 and isl33003 ( figure 3 ) +25 - 86 - s bus idle time t idle ( figure 4 , note 12 )full 50 83 150 s ready pin off state leakage current i off isl33001 only +25 -1 0.1 1 a ready delay, on-off t ready-hl isl33001 only ( note 10 ) +25 - 10 - ns
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 5 of 18 july 11, 2014 ready delay, off-on t ready-lh isl33001 only ( note 10 ) +25 - 10 - ns ready output low voltage v ol_ready v cc1 = +2.5v, i pullup = 3ma; isl33001 only full - - 0.4 v rise-time accelerators transient accelerator current i tran_acc v cc1 = 2.7v, v cc2 = 2.7v ; (acc = 0.7*v cc1 for isl33002 only) ( figure 8 ) +25 - 5 - ma accelerator pin enable threshold v acc_en isl33002 only +25 - 0.5*v cc1 0.7*v cc1 v accelerator pin disable threshold v acc_dis isl33002 only +25 0.3*v cc1 0.5*v cc1 - v accelerator pin input current i acc isl33002 only +25 -1 0.1 1 a accelerator delay, on-off t pdoff isl33002 only ( note 10 ) +25 - 10 - ns esd protection sda, scl i/o pins human body mode l, sda and scl pins to ground only (jesd22-a114) +25 - 12 - kv all pins machine model (jesd22-a115) +25 - 400 - v class 3 hbm esd (jesd22-a114) +25 6 - kv input-output connections input low threshold v il v cc1 = v cc2 , 10k ?? to v cc1 on sda and scl pins +25 - - 0.3*v cc1 v input-output offset voltage v os v cc1 = 3.3v, 10k ?? to v cc1 on sda and scl pins, v input = 0.2v; v cc2 = 3.3v, isl33002 and isl33003 ( figure 5 ) full 0 50 150 mv output low voltage v ol v cc1 = 2.7v, v input = 0v, i sink =3ma on sda/scl pins; v cc2 = 2.7v, isl33002 and isl33003 ( figure 6 ) full - - 0.4 v buffer sda and scl pins input capacitance c in ( figure 25 ) +25 - 10 - pf input leakage current i leak sda and scl pins = v cc1 = 5.5v; v cc2 = 5.5v, isl33002 and isl33003 full -5 0.1 5 a timing characteristics scl/sda propagation delay high-to-low t phl c load = 100pf, 2.7k ?? to v cc1 on sda and scl pins, v cc1 = 3.3v; v cc2 = 3.3v, isl33002 and isl33003 ( figure 7 ) +25 0 27 100 ns scl/sda propagation delay low-to-high t plh c load = 100pf, 2.7k ?? to v cc1 on sda and scl pins, v cc1 = 3.3v; v cc2 = 3.3v, isl33002 and isl33003 ( figure 7 ) +25 0 2 26 ns notes: 8. the algebraic convention, whereby the most negative value is a mi nimum and the most positive a ma ximum, is used in this data sheet. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 10. typical value determined by design simulations. parameter not tested. 11. buffer is in the connected state. 12. isl33002 and isl33003 limits established by characterization. not production tested. 13. if the v cc1 and v cc2 voltages diverge, then the shut down i cc increases on the higher voltage supply. electrical specifications v en = v cc1 , v cc1 = +2.3v to +5.5v, v cc2 = +2.3v to +5.5v, unless otherwise noted ( note 8 ). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol conditions temp (c) min ( note 9 )typ max ( note 9 )units
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 6 of 18 july 11, 2014 test circuits and waveforms figure 3. enable delay ti me figure 4. bus idle time figure 5a. test circuit figure 5b. measurement points figure 5. input to output offset voltage figure 6a. test circuit figure 6b. measurement points figure 6. output low voltage v cc 0v v en v ready v cc 0v 0.5*v cc 0.5*v cc t delay1 - sda_out and scl pins connected to v cc - enable delay time measured on isl33001 only - isl33003 performance inferred from isl33001 v sda_in 0.5*v cc t ready-lh t delay2 - if t delay1 < t en-lh then t delay2 = t en-lh + t idle + t ready-lh - if t delay1 > t en-lh then t delay2 = t en-lh + t ready-lh - v sda_in = v sda_out = v scl_out = v en = v cc v cc 0v v ready v cc 0v 0.5v cc 0.5v cc t idle - en logic input must be high for t > enable delay (t en_lh ) v scl_in - bus idle time measured on isl33001 only - isl33002 and isl33003 performance inferred from isl33001 prior to scl_in transition scl_in sda_in scl_out sda_out v cc1 +3.3v 0.2v 10k 10k 10k 10k gnd 0.2v v in v in scl_in or sda_in scl_out or sda_out v o 0.2v v os = v o - 0.2v scl_in sda_in scl_out sda_out v cc1 +2.7v 0v 900 900 900 gnd 0v 900 scl_out v ol v cc1 sda_out v ol v cc1
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 7 of 18 july 11, 2014 figure 7a. test circuit figure 7b. measurement points figure 7. propagation delay figure 8. accelerator current test circuit figure 9. accelerator pulse width test circuit test circuits and waveforms (continued) scl_in sda_in scl_out sda_out v cc1 +3.3v 2.7k 2.7k 2.7k gnd v in 2.7k 100pf 100pf v in 100pf 100pf scl_in or sda_in scl_out or sda_out *t plh *t phl *propagation delay measured between 50% of v cc1 scl_in sda_in scl_out sda_out v cc1 2.7k 2.7k gnd 2.7k v cc1 2nf 100k i tran_acc = c ? v/ ? t ? v/ ? t is for only the accelerator portion of the waveform scl_in sda_in scl_out sda_out v cc1 10k 10k gnd 10k v cc1 10k * v x * v x * v x < v cc1 (see figure 22 )
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 8 of 18 july 11, 2014 application information the isl33001, isl33002, isl33003 ics are 2-wire bidirectional bus buffers designed to drive heavy capacitive loads in open-drain/open-collector syst ems. the isl33001, isl33002, isl33003 incorporate rise time accelerator circuitry that improves the rise time for systems that use a passive pull-up resistor for logic high. these de vices also feature hot swapping circuitry for applications that require hot insertion of boards into a host system (i.e., servers racks and i/o card modules). the isl33001 features a logic output flag (ready) that signals the status of the buffer and an en pi n to enable or disable the buffer. the isl33002 features two separate supply pins for voltage level shifting on the i/o pins and a logic input to disable the rise time accelerator circuitry. the isl33003 features an en pin and the level shifting functionality. i 2 c and smbus compatibility the isl33001, isl33002, isl33003 ics are i 2 c and smbus compatible devices, designed to work in open-drain/open-collector bus environments. the ics support both clock stretching and bus arbitration on the sda and scl pins . they are designed to operate from dc to more than 400khz, supporting fast mode data rates of the i 2 c specification.in addition, the buffer rise time accelerators are designed to increase the capacitive drive capability of the bus. with careful choosing of components, driving a bus with the i 2 c specified maximum bus capacitance of 400pf at 400khz data rate is possible. start-up sequencing and hot swap circuitry the isl33001, isl33002, isl33003 buffers contain undervoltage lock out (uvlo) circuitry that prevents operation of the buffer until the ic receives the proper supply voltage. for v cc1 and v cc2 , this voltage is approximately 1.8v on the rising edge of the supply voltage. exte rnally driven signals at the sda/scl pins are ignored until the device supply voltage is above 1.8v. this prevents commun ication errors on the bus until the device is properly powered up. the uvlo circuitry is also triggered on the falling edge when the supply voltage drops below 1.7v. once the ic comes out of the uv lo state, the buffer remains disconnected until it detects a valid connection state. a valid connection state is either a bus idle condition (see figure 4 ) or a stop bit condition (a rising edge on sda_in when scl_in is high) along with the scl_out and sd a_out pins being logic high. note: for the isl33001 and isl33003 with en pins, after coming out of uvlo, there will be an ad ditional delay from the enable circuitry if the en pin voltage is no t rising at the sa me time as the supply pins (see figure 3 ) before a valid connection state can be established. coming out of uvlo but prior to a valid connection state, the sda and scl pins are pre-charged to 1v to allow hot insertion. because the bus at any time can be between 0v and v cc , pre-charging the i/o pins to 1v reduces the maximum differential voltage from the buffer i/o pin and the active bus. figure 10. circuit block diagram u1 u2 m1 m2 logic control start-up circuitry precharge circuit rise time accelerator sda_out sda_in v cc1 en v cc2 acc ready u3 u4 m3 m4 scl_out scl_in m5 isl33001 and isl33003 isl33001 only isl33002 only isl33002 and isl33003
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 9 of 18 july 11, 2014 the pre-charge circuitry reduces system disturbance when the ic is hot plugged into a live back plane that may have the bus communicating with other devices. note: for the isl33001 and isl33003 with en pins, the pre-charge circuitry is active on ly after coming out of uvlo and having the device enabled. connection circuitry once a valid connection condition is met, the buffer is active and the input stage of the sda/scl pins is controlled by external drivers. the output of the buffer will follow the input of the buffer. the directionality of the in/out pins are not exclusive (bi-directional operation) and functionally behave identical to each other. being a two channel buffer, the sda and scl pins also behave identically. in addition, the sda and scl portions of the buffer are independent from each other. the sda pins can be driven in one direction while the scl pins can be driven opposite. refer to figure 10 for the operation of the bi-directional buffer. when the input stage of the buffer on one side is driven low by an external device, the output of the buffer drives an open-drain transistor to pull the ?output? pin low. the ?output? pin will continue to be held low by the transistor until the external driver on the ?input? releases the bus. to prevent the buffer from entering a latched condition where both internal transistors are actively pulling the i/o pins low, the buffer is designed to be active in only one direction. the buffer logic circuitry senses, which input stage is being externally driven low and sets that buffer to be the active one. for example, referring to figure 10 , if sda_out is externally driven low, buffer u2 will be active and buffer u1 is inactive. m1 is turned on to drive sda_in low, effectively buffering the signal from sda_out to sda_in. the low signal at the input of u1 will not turn m2 on because u1 remains inactive, preventing a latch condition. buffer output low and offset voltage by design, when a logic input low voltage is forced on the input of the buffer, the output of the buffer will have an input to output offset voltage. the output voltage of the buffer is determined by equation 1 : where v os is the buffer internal offset voltage, r pull-up is the pull-up resistance on the sda/scl pin to v cc and r on is the on-resistance of the buffer?s internal nmos pull-down device. the last term of the equation is the additional voltage drop developed by sink current and the internal resistance of the transistor. the v os of the buffer can be determined by figures 19 , 20 and is typically 40mv. reducing the pull-up resistor values increases the sink current and increases the output voltage of the buffer for a given input low voltage ( figures 17 , through 20 ). rise time accelerators the isl33001, isl33002, is l33003 buffer rise time accelerators on the sda/scl pins improve the transient performance of the system. heav y load capacitance or weak pull-up resistors on an open-drain bus cause the rise time to be excessively long, which leads to data errors or reduced data rate performance. the rise time accele rators are only active on the low-to-high transitions and provide an active constant current source to slew the volt age on the pin quickly ( figure 21 ). the rise time accelerators are triggered immediately after the buffer release threshold (approximately 30% of v cc ) on both sides of the buffer is crossed. once triggered, the accelerators are active for a defined pulse width ( figure 22 ) with the current source turning off as it approaches the supply voltage. enable pin (isl33001 and isl33003) when driven high, the enable pin puts the buffer into its normal operating state. after power-up, en high will activate the bus pre-charge circuitry and wait for a valid connection state to enable the buffer and the accelerator circuitry. driving the en pin low disables the accelerators, disables the buffer so that signals on one side of the buffer will be isolated from the other side, disables th e pre-charge circuit and places the device in a low power shutdown state. ready logic pin (isl33001 only) the ready pin is a digital output flag for signaling the status of the buffer. the pin is the drain of an open-drain nmos. connect a resistor from the ready pin to v cc1 to provide the high pull-up. the recommended value is 10k . when the buffer is disabled by having the en pin low or if the start-up sequencing is not comple te, the ready pin will be pulled low by the nmos. when the buffer has the en pin high and a valid connection state is made at the sda/scl pins, the ready pin will be pulled high by the pull-up resistor. the ready pin is capable of sinking 3ma when pulled low while maintaining a voltage of less than 0.4v. acc accelerator pin (isl33002 only) the acc logic pin controls the rise time accelerator circuitry of the buffer. when acc is driven high, the accelerators are enabled and will be triggered when crossing the buffer release threshold. when acc is driven low, the accelerators are disabled. for lightly loaded buses, having the accelerators active may cause ringing or noise on the risi ng edge transiti on. disabling the accelerators will have the buffers continue to perform level shifting with the v cc1 and v cc2 supplies and provide capacitance buffering. propagation delays on a low-to-high transition, the ri sing edge signal is determined by the bus pull-up resistor, load capacitance, and the accelerator current from the isl33001, isl33002, isl33003 buffer. prior to the accelerators becoming active, the buffer is connected and the output voltage will track the input of the buffer. when the accelerators activate the buffer connection is released and the signal on each side of the bu ffer rises independently. the accelerator current on both sides of the buffer will be equal. if the pull-up resistance on both sides of the buffer are also equal, then differences in the rise time will be proportional to the difference in capacitive loading on the two sides. v out v in v os v cc /r pull-up r on ? ?? ++ = (eq. 1)
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 10 of 18 july 11, 2014 because the signals on each side of the buffer rise independently, the propagation delay can be positive or negative. if the input side rises slowly re lative to the output (i.e., heavy capacitive loading on the input and light load on the output) then the propagation delay t plh is negative. if the output side rises slowly relative to the input, t plh is positive. for high-to-low transitions, ther e is a finite propagation delay through the buffer from the time an external low on the input drives the nmos output low. this propagation delay will always be positive because the buffer connect threshold on the falling edge is below the measurement points of the delay. in addition to the propagation delay of the buffer, there will be additional delay from the different capacitive loading of the buffer. figures 23 and 24 show how the propagation delay from high-to- low, t phl , is affected by v cc and capacitive loading. the buffer?s propagation delay times for rising and falling edge signals must be taken into consideration for the timing requirements of the system. setup and hold times may need to be adjusted to take into acco unt excessively long propagation delay times caused by heavy bus capacitances. pull-up resistor selection while the isl33001, isl33002, isl33003 2-channel buffers are designed to improve the rise time of the bus in passive pull-up systems, proper selection of the pull-up resistor is critical for system operation when a buffer is used. for a bus that is operating normally without active rise time circuitry, using the isl33001, isl33002, isl33003 buffer allows larger pull-up resistor values to reduce sink currents when the bus is driving low. however, choose a pull-up resistor value of no larger than 20k regardless of the bus capaci tance seen on the sda/scl lines. the bus idle or stop bit condition requires valid logic high voltages to give a valid connection state. pull-up resistor values 20k or smaller are recommended to overcome the typical 150k impedance of the pre-charge circuitry, delivering valid high levels.
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 11 of 18 july 11, 2014 typical performance curves c in = c out = 10pf, v cc1 = v cc2 = v cc , t a = +25c; unless otherwise specified. figure 11. i cc1 enabled current vs v cc1 (isl33001) figure 12. i cc1 disabled current vs v cc1 (isl33001) figure 13. i cc1 enabled current vs v cc1 (isl33002 and isl33003) figure 14. i cc1 disabled current vs v cc1 (isl33003) figure 15. i cc2 enabled current vs v cc2 (isl33002 and isl33003) figure 16. i cc2 disabled current vs v cc2 (isl33003) i cc1 (ma) v cc1 (v) 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.02.53.03.54.04.55.05.56.0 t = +85c t = +25c t = -40c v cc1 (v) i cc1 (na) 100 150 200 250 300 350 400 450 500 550 600 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = +85c t = +25c i cc1 (ma) v cc1 (v) 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = +25c t = -40c t = +85c v cc1 (v) v cc2 = 5.5v i cc1 (na) v cc1 (v) 0 10 20 30 40 50 60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = +25c t = +85c v cc2 = 5.5v i cc2 (ma) v cc2 (v) 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = -40c t = +85c t = +25c v cc1 = 5.5v i cc2 (na) v cc2 (v) 0 10 20 30 40 50 60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = +25c t = +85c v cc1 = 5.5v
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 12 of 18 july 11, 2014 figure 17. sda/scl output low voltage vs sink current vs v cc figure 18. sda/scl output low voltage vs sink current vs temperature figure 19. input to output offset voltage vs sink current vs v cc figure 20. input to output offset voltage vs sink current vs temperature figure 21. accelerator pull-up current vs v cc figure 22. accelerator pulse width vs v cc typical performance curves (continued) c in = c out = 10pf, v cc1 = v cc2 = v cc , t a = +25c; unless otherwise 0 20 40 60 80 100 120 061011 v ol (mv) i ol (ma) 12345 789 v cc = 2.3v v in = 0v v cc = 2.7v v cc = 4.5v 0 20 40 60 80 100 120 061011 v ol (mv) i ol (ma) 12345 789 t = +25c t = -40c t = +85c v cc = 3.3v v in = 0v 0 10 20 30 40 50 60 70 80 90 100 v os (mv) i ol (ma) 061011 12345 789 v cc = 2.3v v cc = 3.3v v in = 0.2v v cc = 5.5v 0 10 20 30 40 50 60 70 80 90 100 061011 12345 789 v os (mv) i ol (ma) t = -40c t = +85c t = +25c v in = 0.2v v cc = 3.3v accelerator current (ma) v cc (v) 3 4 5 6 7 8 9 10 11 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = +85c t = +25c t = -40c accelerator pulse width (ns) v cc (v) 200 300 400 500 600 700 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 t = -40c t = +25c t = +85c see figure 9
fn7560 rev 6.00 page 13 of 18 july 11, 2014 isl33001, isl33002, isl33003 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2010-2014. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. figure 23. propagation delay h-l vs v cc figure 24. propagation delay h-l vs c out figure 25. sda/scl pin capacitance vs temperature vs v cc die characteristics substrate and tdfn thermal pad potential (powered up): gnd process: 0.25m cmos typical performance curves (continued) c in = c out = 10pf, v cc1 = v cc2 = v cc , t a = +25c; unless otherwise propagation delay (ns) v cc (v) 0 10 20 30 40 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 r pull-up = 2.7k c in = 10pf c out = 100pf t = +25c t = -40c t = +85c 0 10 20 30 40 50 0 100 200 300 400 500 600 700 800 900 propagation delay (ns) c out (pf) v cc = 3.3v r pull-up = 10k c in = 50pf t = -40c t = +85c t = +25c capacitance (pf) temperature (c) 6 7 8 9 10 11 12 -30 -10 10 30 50 70 90 v cc = 2.3v v cc = 3.3v v cc = 5.5v
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 14 of 18 july 11, 2014 about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 11, 2014 fn7560.6 in ?features? on page 1, changed ?low quiescent current? from ?2.2ma? to ?2.1ma?. on page 4, added ?pb-free reflow profile? entry to ?thermal info? section. in ?electrical spec? table on page 4, changed ?v cc ? to ?v cc1 ? in the ?supply current from v cc2 ? row. in ?electrical spec? table on page 5, for parame ter ?input low threshold?, moved the ?typ? column entry to the ?max? column. on page 6, figure 4, clarif ied the associated notes. on page 7, figure 8, changed ?i acc ? to i tran_acc ?, and noted that the ? v/ ? t is for the accelerator portion of the waveform. december 19, 2013 fn7560.5 added note 13 at the end of the "elec spec" table on page 5 as follows: ?13. if the vcc1 and vcc2 voltages diverge, then the shut-down icc increases on the higher voltage supply." added reference "(note 13)" after "isl33003 only" in rows for vcc1 and vcc2 "shut-down supply current" parameters (last 2 rows of "power supplies" section) on page 4. october 12, 2012 fn7560.4 changed ?sda_in, scl_in...0.3v to +(v cc1 + 0.3)v, sda_out, scl_out...0.3v to +(v cc2 + 0.3)v, enable, ready, acc...0.3v to +(v cc1 + 0.3)v? to ?sda_in, scl_in, sda_out, scl_out, ready...0.3v to +7v; enable, acc...0.3v to +(v cc1 + 0.3)v?, in the absolute maximum ratings section at the top of page 4. removed ?pb-free reflow profile? and link from ?t hermal information? section at the top of page 4. added ?open drain? and ?connect to 10k pull-up resistor to v cc1 .?, in pin descriptions in the ready section on page 3. october 11, 2011 fn7560.3 converted to new datasheet template. changed title of datasheet from: ?2-wire bus buff er with rise time accelerators and hot swap capability? to: i 2 c bus buffer with rise time accelerators and hot swap capability pg 1, added to related literature: an1637, ?level shifting between 1.8v and 3.3v using i2c buffers? replaced pod m8.118 rev 3 with rev 4 due to the following changes: corrected lead width dimension in side vi ew 1 from "0.25 - 0.036" to "0.25 - 0.36" replaced pod m8.15 rev 1 with rev 3 due to the following changes: changed in typical recommended land pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) figure 3 (was fig1) - added: - if tdelay1 < ten-lh then tdelay2 = ten-lh + tidle + tready-lh - if tdelay1 > ten-lh then tdelay2 = ten-lh + tready-lh and replaced graph september 13, 2010 fn7560.2 added soic package information to datasheet for isl33001. april 30, 2010 fn7560.1 changed typical value of ?supply current from v cc1 ? on page 4 for isl33001 only from 2.2ma to 2.1ma. changed typical value of ?input-output offset voltage? on page 5 from 100mv to 50mv. march 18, 2010 fn7560.0 initial release.
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 15 of 18 july 11, 2014 package outline drawing l8.3x3h 8 lead thin dual flat no-lead plastic package (tdfn) rev 0, 2/08 bottom view top view side view detail x typical recomme nded land pattern located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be measured between 0.15mm and 0.30mm from the terminal tip. lead width dimension applies to the metallized terminal and is dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 8 5 1 4 see detail "x" 0 .80 max ( 6x 0 . 5 ) 2 . 80 ( 2.38 ) 8x 0.60 seating plane c 0.2 ref 0 . 05 max. 0 . 00 min. c 0.08 base plane c 0.10 c pin #1 index area 6 (4x) 0.15 pin 1 index area 3.00 b 3.00 a 6 6 x 0.50 8 x 0.25 c 0.10 m b a 8 x 0.40 1.50 ref ( 1.64 ) 2.38 1.64 2.20 ( 8x 0.25 ) ( 2 .20 )
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 16 of 18 july 11, 2014 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 17 of 18 july 11, 2014 package outline drawing m8.118 8 lead mini small outline plastic package rev 4, 7/11 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.36 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
isl33001, isl33002, isl33003 fn7560 rev 6.00 page 18 of 18 july 11, 2014 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or ga te burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 3. package width does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are s hown for reference only. 6. the lead width as measured 0.36m m (0.014 inch) or greater abo ve the seating plane, shall not exceed a maximum value of 0.61mm (0.02 4 inch). 7. controlling dimension: millimete r. converted inch dimensions a re not necessarily exact. 8. this outline conforms to je dec publication ms-012-aa issue c . side view a side view b 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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